Conventional interconnect structures for integrated circuits are often formed using aluminum as a metallization and silicon dioxide as a dielectric. However, while integrated circuits are being continuously scaled down (such as device scaling from the 90 nm node to the 65 nm node and further to the 45 nm node), conventional interconnect structures often suffer from an interconnection delay due to high electrical resistance and parasitic wiring capacitance. These problems are major factors that limit the speed of high performance integrated circuits.
Because of these problems, integrated circuit manufacturers have begun using copper in place of aluminum and a low-K material in place of silicon dioxide in the interconnect structures. The copper helps to lower the resistance of the interconnect metallization and increase the reliability of the interconnect structures, while the low-K material helps to reduce the parasitic capacitance between the interconnect structures by providing a lower dielectric constant.
A problem with these types of interconnect structures is that low-K materials are often mechanically weak, but the interconnect structures often experience high strain or stress when the integrated circuits undergo further processing. For example, the interconnect structures may experience compressive force during a wire bonding process or after epoxy encapsulation, or the interconnect structures may experience shear stress after a flip chip attach. These strains or stresses could cause damage or destruction of the interconnect structures, such as by causing the low-K material to collapse or by causing interfacial delamination of the copper and the low-K material.